In the last time, Verilog becomes quite popular among Hackers – based on the hype the FOSS Yosys Toolchain kicked off for the iCE40 FPGAs.
It is a known fact, that everybody can learn faster from someone which already did the stuff more than once. While freelancing in Chip Design for two decades I like to share Design Pattern in Verilog.
Design Pattern means,
– styleguides which results in readable code,
– how to write good and fast Finite State Machines, why they are so useful,
– how to deal with clock-domain crossing and why we might need that,
– how to structure your source code design files,
– how to use Makefiles for that,
and much, much more.
All with code snippets to show and explain.
I can’t be stopped, until the time slot is closed.
- GPN18 – Hacking relationships - 15.05.2018
- GPN18 – automated number plate readers - 15.05.2018
- GPN18 – U2Fishing: Potential Security Threat Introduced by U2F Key Wrapping Mechanism - 14.05.2018
- GPN18 – ada_conf – the making of a separatistic IT conference - 14.05.2018
- GPN18 – Infrastructure Review and Closing - 14.05.2018